(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of using photoresist whereby photoresist patterning and processing results are not dependent on the thickness of the layer of photoresist.
(2) Description of the Prior Art
Semiconductor device performance continues to be improved by a further reduction in device dimensions. Smaller device dimensions can only be achieved by creating semiconductor devices with smaller and smaller device feature sizes. Included in the continuous reduction of device feature sizes are such device aspects as reducing the spacing between interconnect lines, reducing the width of the interconnect lines, while also affecting feature geometries such as the profiles of cross sections of device features such as isolation regions, via interconnect openings and trenches for interconnect traces.
Problems that are encountered by further decreasing device dimensions are problems imposed by the process of photolithography that is most typically used for the creation of device features. Photolithography is the process whereby a pattern, typically created on the surface of an exposure mask, is transferred to a layer of photoresist. The layer of photoresist (functioning as a radiation sensitive layer of semiconductor material) is uniformly coated over a semiconductor surface, such as the surface of a silicon substrate, after which an exposing source of energy such as optical light, X-rays or an E-beam apparatus) illuminates selected surface areas of the layer of photoresist, preparing this layer of photoresist for selectively being removed from the semiconductor surface. The remaining photoresist comprises, in sharply reduced form, the pattern that is contained on the surface of the exposure mask.
The process of photolithography is an essential process for the creation of semiconductor devices and has, with the evolution of semiconductor devices, seen numerous improvements in its ability to provide desired exposure capabilities that meet current and evolving semiconductor device processing requirements. With further reduction in devices feature dimensions, increased emphasis is placed on focusing resolution and depth of focus of the exposing energy. Some of these problems have been addressed by decreasing the wavelength of the exposing energy source or by increasing the energy of the exposure source or by increasing the time of exposure. With device feature size approaching dimensions of about 0.25 μm or less, acceptable image resolution becomes ever more difficult to achieve. The essential reason for this is that the thickness of the layer of photoresist, which is used for image creation, is typically about 7,000 Angstrom, which inhibits the possibility of creating a sub-micron pattern that has the desired feature resolution. It would therefore appear that this problem could be addressed by reducing the thickness of the applied layer of photoresist. This approach however in turn introduces problems of creating a desired profile of the cross section of the created device features, whereby for instance undesirable corner rounding of this profile becomes an issue. In addition, a thinner layer of photoresist leads to reduced etch protection for an underlying layer of semiconductor material during the process of etching the pattern that is contained in the layer of photoresist into this underlying layer.
It is therefore desired to provide a process or method of photolithographic exposure that results in improved pattern resolution and in improved control of the Critical Dimensions (CD) of the pattern that is being created. The invention provides such a method and procedure.
U.S. Pat. No. 6,248,635 (Foote et al.) shows a dual layer HM and etch process.
U.S. Pat. No. 6,200,907 (Wang et al.), U.S. Pat. No. 6,171,163 (Wang et al.) and U.S. Pat. No. 6,156,659 (Wang et al.) are related dual HM and ARC etch processes.
U.S. Pat. No. 6,069,091 (Chang et al.) shows a Si containing hardmask plasma etch method. This does not have an organic ARC layer and does not remove PR before the etch.
U.S. Pat. No. 6,030,541 (Adkisson et al.) shows a process to pattern an ARC and structure. However, this uses a wet HM etch and does removes the PR before the Poly etch.